1. Field
The present invention relates to technology for a semiconductor device, and relates to technology effective for example in semiconductor devices containing a semiconductor chip mounted over a wiring substrate having plural stacked wiring layers.
2. Related Art
Signal transmission paths to electrically couple circuits formed over the semiconductor chip and external devices are formed over the wiring substrate where the semiconductor chip is mounted. To render the impedance discontinuities formed over these signal circuit paths harmless a discontinuity cancellation technology is employed that cancels the impedance discontinuity by utilizing an inverse impedance discontinuity.
A technology is disclosed for example in Japanese Unexamined Patent Application Publication No. 2004-253947 (patent document 1) in which a third planar circuit having a characteristic impedance higher than a first planar circuit; and a fourth planar circuit having a characteristic impedance higher than a second planar circuit are serially coupled between a first planar circuit, and a second planar circuit having a higher characteristic impedance than the first planar circuit.
Also, the non-patent document 1 for example discloses a technology for matching an average impedance to a 50 ohm impedance by enclosing the front and back of a low-impedance section configured from a through via and a solder ball pad by a high-impedance line.
The non-patent document 2 for example discloses technology for matching an average impedance in a signal transmission path including a low-impedance section configured from a through via and a solder ball pad to a 50 ohm impedance by way of a conductor layer formed in a inductor configuration by combining a small via and a wiring pattern.
[Non-Patent Document 1]
    Nanju Na, Mark Bailey and Asad Kalantarian, “Package Performance Improvement with Counter-Discontinuity and its Effective Bandwidth”, Proceedings of 16th Topical meeting on Electrical Performance of Electronic Packaging, p. 163 to p. 166 (2007)[Non-Patent Document 2]    Namhoon Kim, Hongsik Ahn, Chris Wyland, Ray Anderson, Paul Wu, “Spiral Via Structure in a BGA Package to Mitigate Discontinuities in Multi-Gigabit SERDES System”, Proceedings of 60th Electronic Components and Technology Conference, p. 1474 to p. 1478 (2010)